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Honored Contributor
Honored ContributorEMIF SDRAM Clock Domain Inquiry
Hi, My goal is to interface my FPGA design with an external DDR3 SDRAM memory using the EMIF IP. I am working off of a sample design, which provided all the parameters for the EMIF (memory clo...
Altera_ForumHonored Contributor
Honored ContributorHi,
--- Quote Start --- My question is as follows: What is the best practice if I want to operate my FPGA design at a different frequency than 266MHz? --- Quote End --- Based on datasheet parameters select frequency and use PLL also take care of Timing closer. --- Quote Start --- Should I treat the EMIF as if it belongs to a different clock domain and use clock domain crossing techniques? Is it possible to run the DRAM at a lower memory clock frequency? Or is there a better solution? --- Quote End --- Yes can use, Subjected to the datasheet, But Certain frequencies of operation give you the best possible latency based on the memory parameters, You can check the specification of DDR3 and select the frequency required for optimal performance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
