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New ContributorEMIF Avalon-MM Burst never ending
Hello, I try to write data to "EMIF Intel Arria 10 FPGA" (for DDR4 SDRAM) component with avalon-mm burst. If this works for burstlenght of 1, it doesn't for 2 or more. It means that if I try to wri...
Hi,
I think the busrtbegintransfer signal no longer used in Arria 10 device.
The signal exist to support legacy memory controllers.
Most of the avalon interfaces got some details in the Avalon Interface Specifications: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/memory-mapped-interface-signal-roles.html
About the clocks, the PLL_REF_CLK should be the clock source for EMIF IP.
The EMIF IP can provide the clock to user logic through the EMIF_USR_CLK.
You may feed your logic with this clock.
The chip select for EMIF interface is between FPGA and external memory.
https://www.intel.com/content/www/us/en/docs/programmable/683106/21-1-19-2-0/mem-for-ddr4.html
Regards,
Adzim
