BKB
Occasional Contributor
Occasional ContributorEMIF - ref_clk from a bank other than address control and share that ref clock for 2 EMIF instances
Hi, I am using a Stratix 10 1SG10MHN3F74C2LG dual die FPGA on our board. Each die has two EMIF instances. Each EMIF instance uses reference clock fed from the clk pins in the address control IO Ban...
Hi Bharat,
Unfortunately, the ref_clk need to be placed within the Address and Command group.
Sharing the pin to other EMIF IP is permitted but need to follow the rules.
Regards,
Adzim
