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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

EMIF - ref_clk from a bank other than address control and share that ref clock for 2 EMIF instances

Hi, I am using a Stratix 10 1SG10MHN3F74C2LG dual die FPGA on our board. Each die has two EMIF instances. Each EMIF instance uses reference clock fed from the clk pins in the address control IO Ban...
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  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    1 year ago

    Hi Bharat,


    Unfortunately, the ref_clk need to be placed within the Address and Command group.

    Sharing the pin to other EMIF IP is permitted but need to follow the rules.


    Regards,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi Bharat,


Unfortunately, the ref_clk need to be placed within the Address and Command group.

Sharing the pin to other EMIF IP is permitted but need to follow the rules.


Regards,

Adzim


  • BKB's avatar
    BKB
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Thanks Adzim,

    Best, Bharat