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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
9 months ago
Solved

EMIF - ref_clk from a bank other than address control and share that ref clock for 2 EMIF instances

Hi, I am using a Stratix 10 1SG10MHN3F74C2LG dual die FPGA on our board. Each die has two EMIF instances. Each EMIF instance uses reference clock fed from the clk pins in the address control IO Ban...
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  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    8 months ago

    Hi Bharat,


    Unfortunately, the ref_clk need to be placed within the Address and Command group.

    Sharing the pin to other EMIF IP is permitted but need to follow the rules.


    Regards,

    Adzim


sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
9 months ago

Have you tried using Interface Planner in Quartus to see if this is possible? That would be the easiest way to see without having to wait for a full compilation.

  • BKB's avatar
    BKB
    Icon for Occasional Contributor rankOccasional Contributor
    9 months ago

    I had tried implementation with the pinout as desired and it did nor work. Hence I had posted here if there was a workaround.
    I did try the interface planner after your suggestion and got the errors there too.

    If there was a way to to make it work, as I had described in the original post. please let me know.

    Best,

    Bharat