Occasional Contributor
Super ContributorI'm assuming you are targeting a device that supports "current" PR (Cyclone 10 GX, Arria 10, Stratix 10) and that you are using the Pro edition of Quartus.
1) Yes, on-chip memory should initialize like other registers on power-up without initialization: all 0's. However, if you want to guarantee this, you should add memory reset code to your design to blank out the RAM (a for loop that runs on reset).
2) No. The freeze signal is generated in the static region (normally by the region controller IP) so it is always correct. And the freeze signal only feeds logic in the static region, not the PR region. The option you mention (which I had not seen before) is meant for initialized RAM that is put in the PR region to prevent issues with the initialization of the contents of that RAM, not in the static region. Check out page 22 of the PR user guide for the circuit I'm guessing this option is implementing: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-pr.pdf
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