Forum Discussion
kokodo
New Contributor
New ContributorE-Tile Transceiver Native PHY Intel Agilex FPGA IP refclk error
Hello, I would like to use PIN_CE18 for E-TILE transceiver 156.25M reference clock input,but these error messages appear.I have tried using a iopll fpga ip out clock as a reference clock,it made a s...
Hi,
As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you,
Kshitij Goel
Kshitij_Intel
Frequent Contributor
Frequent ContributorHi,
Can you please share which Quartus version and device you are using?
Also, you can refer to the Error(175020): The Fitter cannot place logic pin that is part of... (intel.com)
Error (175020): Illegal constraint of PLL output counter to the... (intel.com)
Hope this helps.
Thank you,
Kshitij Goel
