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alexforencich's avatar
alexforencich
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

E-Tile PTP timestamping issues

I am running into some odd issues with PTP timestamping on the E-Tile on both Stratix 10 DX (Intel S10 DX dev kit) and Agilex F (DE10-Agilex). Ultimately, what I want to be able to do is run a bun...
paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi Alex,


I have read through your prompt explanation. Did you try to generate example design based on your IP setting?

If no, I would suggest you to generate design example and compare with your current design. It will help us to find the missing piece between the design example and your own design.


Regards,

Pavee


alexforencich's avatar
alexforencich
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I can generate one, but what should I be looking for?

Anyway, the full project source code is here: https://github.com/alexforencich/corundum/tree/master/fpga/mqnic/DE10_Agilex/fpga_25g

The exported IP TCL files are here: https://github.com/alexforencich/corundum/tree/master/fpga/mqnic/DE10_Agilex/fpga_25g/ip . Both the 10G and 25G variations present the same issue.

The E-Tile MACs are instantiated in this module: https://github.com/alexforencich/corundum/blob/master/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/eth_mac_dual_quad_wrapper.v