Occasional Contributor
Frequent ContributorHi Alex,
I have read through your prompt explanation. Did you try to generate example design based on your IP setting?
If no, I would suggest you to generate design example and compare with your current design. It will help us to find the missing piece between the design example and your own design.
Regards,
Pavee
Occasional ContributorI can generate one, but what should I be looking for?
Anyway, the full project source code is here: https://github.com/alexforencich/corundum/tree/master/fpga/mqnic/DE10_Agilex/fpga_25g
The exported IP TCL files are here: https://github.com/alexforencich/corundum/tree/master/fpga/mqnic/DE10_Agilex/fpga_25g/ip . Both the 10G and 25G variations present the same issue.
The E-Tile MACs are instantiated in this module: https://github.com/alexforencich/corundum/blob/master/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/eth_mac_dual_quad_wrapper.v
