Forum Discussion
Hi HPB,
Sorry for the delay in respond as I am quite tie up last week.
Now I understand better your concern on PMA and PCS bonding master channel selection. 4 lanes protocol should be fine but 2 lanes protocol is a challenge in flip orientation condition.
DP example design recommend to set lane 0 as master bonding channel for ease of channel placement management. master channel lane 0 will fit just fine for both 2 lanes and 4 lanes protocol
- 4 lanes protocol : lane 0 (master) + lane 1 (slave) + lane 2 (slave) + lane 3 (slave)
- 2 lanes protocol : lane 0 (master) + lane 1 (slave)
But now if I understand you correctly, type-C connector will flip the channel orientation to using lane 2 and lane 3 for 2 lanes protocol ?
- Meaning lane 0 and lane 1 becomes unused.
- If NativePHY still configure lane 0 as master channel while actual data traffic go through lane 3 and lane 4 then the functionality will fail.
This type-C connector flip really complicated everything
- Other than our previous discussion talked about adding mux to re-route the data traffic between transceiver channel and DP sink but now looks like you need to dynamic reconfigure transceiver channel bonding master channel selection as well to make it to work for 2 lanes protocol , right ?
You are our first customer asking about type-C connector support so I can only try my best to analyze the situation together with you.
- In short, for flip condition
- first of all, You need to have some mechanism to be able to detect the channel is already flip
- Second, you need to reconfigure transceiver channel + switch data muxing logic
Is my understanding correct ? I believed this is the reason you are asking about bonding master channel question in the first place ?
Thanks.
Regards,
dlim
- HBhat25 years ago
Contributor
Hi @DeshiL_Intel ,
Thanks for your in detail analysis.
"
But now if I understand you correctly, type-C connector will flip the channel orientation to using lane 2 and lane 3 for 2 lanes protocol ?
Meaning lane 0 and lane 1 becomes unused.
"
Yes, this happens during 2-lane DP mode. otherwise (4-lane DP) During Flip, Lane-0 will become Lane-3, Lane-1 will become lane-2 and vice versa. (All channels will be used both in flip & no flip mode.
"
If NativePHY still configure lane 0 as master channel while actual data traffic go through lane 3 and lane 4 then the functionality will fail.
"
Ok, to have the proper data we need to dynamically reroute the data stream from DP encoder to corresponding PMA/native phy instances (as shown in the snapshot with previous reply)
"
Other than our previous discussion talked about adding mux to re-route the data traffic between transceiver channel and DP sink but now looks like you need to dynamic reconfigure transceiver channel bonding master channel selection as well to make it to work for 2 lanes protocol , right ?
"
Yes, this is what I want to know whether I can change the master PCS channel dynamically (using dynamic reconfiguration).
"
You are our first customer asking about type-C connector support so I can only try my best to analyze the situation together with you.
- In short, for flip condition
- first of all, You need to have some mechanism to be able to detect the channel is already flip
"
We have external logic / additional circuit to detect the flip condition or normal (no flip condition)
"
- Second, you need to reconfigure transceiver channel + switch data muxing logic
I believed this is the reason you are asking about bonding master channel question in the first place ?
"
Yes.
So, I need to see how we can change the master PCS channel in dynamic reconfiguration.
If you have came across any reference design or any material reference to change the master PCS channel through dynamic reconfiguration, please share with me.
With Regards,
HPB