Dual Port RAM

I think that inside the memory the address is latched not registered which means the address flushes through the latch while the clock is high and on through the decoders then on to q. The latches are then held when the clock is low so that q can be registered at the next clock and the delay through the ram provides the hold time for the register. q async changes shortly after the clock. (The time is the ram access time)

So the address in can come from a posedge register, flush thru the latches and decoders then on to produce q async (wo reg). The latches are then held until the next clock when the the operation repeats.

The path length is ram access time + external logic delay for any logic driven by q.