Dual port RAM shared between Nios and async interface

After reading this post and other related posts I decided to stay away from using Dual port RAM shared between Nios and async interface in QSYS.

If not for BadOmen's advice, then You never know what could be the problem.

To start with I decided to try this reliable approach:

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The current (working) implementation was:

- sopc system with Nios and pio bus

- external lpm ram component in dual port mode.

- Nios accesses ram through pio bus

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To learn how to do it correctly from the start I would like to learn the way You did it although it might seem simple.

Would You please publish it?