Dual port RAM shared between Nios and async interface

The nios tightly coupled data interface does use the clock enable signal (to hold the read data from the previous address when the cycle before that stalls the cpu on an avalon tranfser).

So there is some lurking support for it in sopc/qsys.

Using the clock enable also stops sopc from selecting single clock mode, whereupon it silently ignores the OLDDATA flag.

(In single clock mode 'clock enable' is replaced with the inverted 'address hold').

The fact that the commented out lines of all the sopc generated files are the ones that are used is somewhat confusing - caused us much confusion.