Dual port RAM shared between Nios and async interface

You are welcome. Also as a heads up I discourage people from using the synthesis translate on/off attributes in verilog/VHDL. That is what causes the comment lines from being used as the synthesis source, so I don't recommend doing that because it's confusing. When you write your HDL if you want to have seperate synthesis and simulation code I would split those out into two file sets instead, this is much cleaner in Qsys as well.