Dual port RAM shared between Nios and async interface

Ahhhh I see the problem. In the verilog file the first clock enable is not getting hooked up (clock enable isn't part of the Avalon specification). Quartus II grounds disconnected inputs so the memory port had it's clock enable stuck low. The simple fix would be change this line (it's the comment line because that's what actually gets synthesized):

// .clocken0 (clken),

to

// .clocken0 (1'b1),

Since you generated this verilog from SOPC Builder I'm not sure what it did with that clock enable. I have been using SOPC Builder since it was first released and I don't remember clock enable being part of the Avalon-MM specification so there must have been an extra layer of extraction involved. Also it probably would be cleaner to just write verilog by hand than use machine generated code. Signals like chip select and clock enable are not necessary signals so you could have left them out if you coded the file by hand.