Dual port RAM shared between Nios and async interface

The read latency of the slave port that you connected to the CPU is wrong in the .tcl file:

"set_interface_property avalon_slave_0 readLatency 0"

Based on the verilog parameterization of the memory you should set that read latency to 1. There is a input register stage inside the RAM block and the output is not registered so it so the total read latency is 1 for this setup.

By the way if you used Qsys you wouldn't need to do all this stuff to expose one of slave ports of the memory to the top level, you would just click on the 2nd slave port and tell Qsys to export it.