Dual port RAM shared between Nios and async interface

Hi, I did not want to create a new thread because I have a very similar problem with my dual port RAM which is shared between NIOS and my async interface. Please let me know if I need to create another thread.

First, I am using Quartus II 9.0 SP2 with a CIII device with Nios. I currently need the Nios to write data into a dpram and then my verilog logic block to access the ram to read the data in a different clock domain.

The current (working) implementation was:

- sopc system with Nios and pio bus

- external lpm ram component in dual port mode.

- Nios accesses ram through pio bus

- my verilog logic will access the external lpm ram directly to read.

To have a cleaner solution, I'd like the Nios to access the dpram directly with Avalon bus.

Following this thread, I added a new onchip ram component with dual-port enabled from SOPC builder. Then using the "new component", I used the conduit to export all I/Os of one port and connected the other port to all "avalon_slave" (clk was to clk_sink). I did not add a avalon master because I still do not understand how that plays a role.

Then, I had to tie these pins at the SOPC block diagram:

inputs

address2_to_the_dual_port_ram_0[10:0] = verilog logic addr output

byteenable2_to_the_dual_port_ram_0[3:0] = pulled high

chipselect2_to_the_dual_port_ram_0 = pulled high

clk2_to_the_dual_port_ram_0 = clk

clken2_to_the_dual_port_ram_0 = pulled high

write2_to_the_dual_port_ram_0 = pulled low

writedata2_to_the_dual_port_ram_0[31..0] = pulled low

outputs

readdata2_from_the_dual_port_ram_0[31..0] = verilog logic read data input

After compilation, I created a new NIOS project and tried to write 0xAB to the ram.

int a;

IOWR(DUAL_PORT_RAM_0_BASE, 0, 0xAB);

a = IORD(DUAL_PORT_RAM_0_BASE, 0);

In debug mode, "int a" is always 0.

I must be missing something. Attached is my .v and .tcl files.

PS, I also tried adding a new on-chip ram component with only single port to see if I could just write to it. But during NIOS initialization through JTAG, the processor paused with an error. I am not sure why.