Dual port RAM shared between Nios and async interface

Hi HJS,

I implemented your solution and it works perfectly! Thank you again.

Could you answer one last question? Just because I read Avalon specification but I'm not sure if I understood everything.

Following your hints, I now have a sopc system exporting address,be,cs,rd,wr,writedata input signals and readdata,waitrequest output signals. Connecting to these signals my external processor can now rd/wr data on the onchip dpram.

Suppose now the bus I connect to needs arbitration, for example because I connected to a multi master bus, or the main Avalon bus, as I asked in the question above.

Point 1 is ok: host processor is sync to Avalon clock domain

Regarding point 2, is the waitrequest signal enough to manage master accesses?

I mean, should host processor simply drive cs, rd or wr, be, addr signals and hold until waitrequest signal is asserted or a more complex handshake logic may be required?

I want I minimal implementation, then no arbiterlock, pipeline or burst functions

Regards

Cris