Dual port RAM shared between Nios and async interface

Ok. I got it. It was easier than I expected.

Before your hints I missed it because I thought I had to explicitly expose signals I wanted to export, which I couldn't do with onchip ram sopc component. Adding the "fake" component with master interface does the trick.

I'll test both solutions and I'm confident at least one of them will do the job.

Bonus question:

Now my external master is supposed to access only one dpram port, while Nios master accesses the other side.

I wonder if I can use the same component to allow the dsp or any other host processor to access the main Avalon bus

(I don't need this now; just an idea for future projects)

Thank you again HJS