DSP CIC problem

Hello,

I am observing a strange (to me) behaviour with a CIC IP instantiated in dsp builder (12.1sp2).

I am using it to decimate a 10 MSample/sec signal to 100 KSample/sec.

I used the following parameters:

Filter type: Decimator

Number of stages: 3

Differential delay: 1

Rate change factor: 100

Variable Rate Change Factor Options (disactivated)

Number of interfaces: 1

Number of channels per interface: 1

Input data width: 16 bits

For the output I’ve tried to use also full output resolution, but the "problem" is still present.

If I use more than 3 or 4 bits for the amplitude of the input signal (signed), then I obtain the results I expect, but with less bits no.

If I use a 10 KHz signal as input I obtain the output as I expected (a 10KHz sampled at 100 KSample/sec) even with one only bit of amplitude, but with a 1 KHz signal the output is different (it seems somehow distorted).

Please have a look at the screenshots present in the attachment.

I find this behaviour very strange; probably there is some DSP reasoning I am ignoring. Maybe in order to obtain the expected results even with a 1 KHz tone I should configure the CIC differently or use it with some workaround.

Any advice is more than warmly welcome.

A_G76