Honored Contributor
Honored ContributorI forgot to ask earlier, does simulation work for you in 2006a? The first thing Signal Compiler and TestBench does is to try and resolve the types in your design. It does this by doing the equivalent of Ctrl+D (update diagram) on your design.
If this step fails then there might be problems. If you can simulate a design without any error messages then this is not likely to be the problem. After it finds all the port sizes, it creates a file called <model>.mdlxml where <model>.mdl is the name of your model file. Does this file exist?
