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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

DSP Builder Advanced: integrator and differentiator blocks

Hello!

I need to construct integrator and differentiator blocks in advanced blockset, so I need some delay to store previous data. I don't know how to do this, because there is different latency of blocks and there are errors about combinational loops. I think I could use valid signal, but don't know exactly how. And another problem is that sample time and clock frequency are different in my design. Help needed.

Thank you.

1 Reply

  • seb_'s avatar
    seb_
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hello everyone

    I am still facing the problem. I want to implement an integrator. My approach is "forward euler" y[n] = y[n-1] + T u[n-1]. But I can not figure out how to choose the step length T. It is not 1/systemClockRate. What is it else?

    What delay/latch is the most feasible one and how can I trigger the enable port? Is there a way to build an impulse generator?

    Thank you very much