Forum Discussion
Navaneeth
New Contributor
New ContributorDSP Block Stratix 10 - Multiply Accumulate
Hi We wish to perform c = c + (a * b) where,
a, b and c are 32-bit unsigned numbers.
Please let us know how best to implement this multiply-accumulate in Verilog so that the DSP blocks avail...
Hi,
You can also check the full design template within Quartus.
Thank you
Kshitij Goel
NavaneethNew Contributor
New ContributorHi,
Thanks for the reply.
We modified our Verilog code and introduced registers at the appropriate places by looking at the circuit diagram of the 'Native Fixed Point DSP Intel Stratix 10 FPGA IP'. The latency from input to output is 5 clock cycles with the modified code. Now, Quartus is saying that all the DSP blocks, that it is inferring, are fully utilizing the recommended internal register banks.
Please find the modified MAC unit Verilog code:
Please do suggest further improvements, if any, to achieve higher Fmax.
