Doing a 32-bit access through an Avalon 32-bit Bridge to a 16-bit wide Avalon MM SDRAM Controller slave doesn't seem to follow the Avalon Dynamic Bus Sizing in my QSYS design.

Hello KTan, Here is a zoomed out view of the SignalTap capture: Below in the zoomed-in view you can see the 32 bit data at the Qsys Port presented at the top level of the FPGA design. The Bus Cycle is being held until completion by the Qsys "External to Avalon Bridge" by using the "acknowledge" signal. When it is asserted you can see that the Qsys design has merely duplicated the 16 bit value on the lower part of the data bus to the upper part of the data bus. I was expecting the Qsys Avalon fabric to do the Dynamic Bus Sizing (as explained in the Avalon Bus Spec). I was expecting the Qsys Avalon fabric to do the Dynamic Bus Sizing (as explained in the Avalon Bus Spec). Here are some further screenshots of my Qsys Design: This is the Bridge Master with the 4 Byte Enables, 32 bit data width: This is the SDRAM Controller Slave: This is the QSYS design showing the internal mm interconnections hookup: I appreciate your prompt attention to this matter. Charles On 2018-09-05 22:19, Intel Forums wrote: Links: