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mnazemi's avatar
mnazemi
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6 years ago

Does Intel HLS Compiler combine or split variables?

Assume I have a component which includes something like the following lines: bool input_0; bool input_1; bool input_2; bool input_3; bool wire_0; bool wire_1; bool output_0; wire_0 = input_0 ...
MEIYAN_L_Intel's avatar
MEIYAN_L_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi,

Have you try to compile the code in HLS? The project directory (.prj) will be created after compilation. You can open the design and see the RTL generated.

Thanks

  • mnazemi's avatar
    mnazemi
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    6 years ago

    Obviously, I have done that. But I am not able to find the corresponding Verilog code under components directory.