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DWhit11's avatar
DWhit11
Icon for New Contributor rankNew Contributor
6 years ago

Does a slow Avalon slave block the Lightweigh HPS-to-FPGA bridge?

We have multiple Avalon slave devices running off the Lightweight bridge on a Cyclone V. One device is fairly slow and has to do long block transfers (32 bit transfers at a time). The IP holds waitre...
FawazJ_Altera's avatar
FawazJ_Altera
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello,

The H2F lightweight bridge can support single and multiple transaction/s. There is a master unit called Global Programmer's View (GPV) which controls the interface bridges. The GPV allows you to set the bridge’s issuing capabilities to support single or multiple transactions. The GPV also lets you set a write tidemark through the wr_tidemark register, to control how much data is buffered in the bridge before data is written to slaves in the FPGA fabric.

You can refer to this document :

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_54001.pdf#_OPENTOPIC_TOC_PROCESSING_d83e229134

page (9-35)

Thank you