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LGonz14's avatar
LGonz14
Icon for New Contributor rankNew Contributor
6 years ago

Documentation for Cyclone 10 GX core components?

Using the mega-function wizard, I'm generating a GPIO IP in DDIO register mode. The mega-function wizard generated several files, among them altera_gpio.sv was found. Within this module, an instance ...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Luis,

Please allow me to clarify. So you are connecting the PHY transceiver instance IP to this GPIO IP in FPGA?

If it so, it cannot be. This IP is meant for connecting with input/output from external devices.

Thank You.