Forum Discussion

New Contributor

6 years ago

Documentation for Cyclone 10 GX core components?

Using the mega-function wizard, I'm generating a GPIO IP in DDIO register mode. The mega-function wizard generated several files, among them altera_gpio.sv was found. Within this module, an instance ...

KennyT_altera

Super Contributor

6 years ago

Hi Luis,

You can refer to here https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf

What IO standard that you were using for the GPIO pin?

Forum Discussion

Documentation for Cyclone 10 GX core components?

Recent Discussions

Agilex 7 slew rate reconfiguration

Agilex-7 AXI MCDMA for PCIe hang

Constraints not being picked for DCFIFO

Can't generate F-Tile Ethernet Hard IP Design Example

MAX10 TSE reference design