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lcy2000's avatar
lcy2000
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2 years ago

Do arria 10 avst Configuration Space Bypassed Root Port still has a virtual pci bridge

Hello, I'm using the Arria 10 Avalon Streaming PCIe IP as a root port, which Configuration Space Bypass enabled. I'm confused that is there still a virtual pci bridge beneth the avst port, awaiting ...
Pcie
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Lcy2000,


When the Configuration Bypass (CfgBP) parameter is enabled, the Configuration Read/Write TLPs are output to the user side. The CfgWr1 and CfgRd1 TLPs are sent from the Root Port to the application layer, so the user circuit has to respond to those TLPs correctly.


In Configuration Bypass Mode, the hard IP passes all well-formed TLPs to the Application Layer using the Avalon-ST RX interface. The hard IP detects and drops malformed TLPs. Application Layer logic must detect and handle Unsupported Requests and Unexpected Completions. Application Layer logic must also generate all completions and messages and transmit them using the Avalon-ST TX interface.


I would suggest you to refer Stratix V Avalon-ST Interface for PCIe Solutions: User Guide for more information on Configuration Bypass.

https://www.intel.com/content/www/us/en/docs/programmable/683093/15-1/configuration-space-bypass-mode.html


Thanks.

Best Regards,

Ven