DMA & FIR Filter, some questions.

Looks like a cache coherency problem to me. If you have a data cache enabled for the CPU then when you write to the "From value" it might be in the data cache. Nios II implements a write back cache which means the data will only arrive at the memory when the line is evicted as a result of a miss or it is flushed. Either remap those pointers to be uncacheable or flush the data cache before triggering the DMA so that the contents will be written out to memory before the DMA attempts to move the data.