DMA & FIR Filter, some questions.

The accelerated FIR design is pretty old so I would only use it as a reference if you decide to build a FIR that has masters sticking out of it. I also don't recommend this as it makes doing verification more difficult (easier when each block is separate).

The master templates are old as well and use a custom handshaking between the user logic and the master. It could be that the handshake between your logic and the master template is not timed correctly. As an FYI one of these days I plan on removing those master templates on the web and replacing them with the masters from the modular SGDMA and some simple handshake blocks that you can export to the top so if you can't find them check alterawiki.com since that is where I'll put them.

I don't use DSP Builder myself since I'm an embedded guy, but I would think you want to verify the filter logic using the DSP tools and DMA logic using the SOPC Builder tools separately. Again this is easier to do when the functionality is separated using multiple components that use standard interfaces. SOPC Builder is also capable of outputting simulation files so that you can simulate the system (including Nios II code running on the processor).