DisplayPort

Hi Tricky,

I Have read the user guide of DP and the specification of VESA to be able to implement this IP in my own design. I was able to run the design simulation of altera with modelsim.

After that I created my owne design (DP-Sink plus thiers PHY and XCVR). The compilation passe without any error. But when I started the simulation of this design I have many error.

1- When I take a look into the DISPLAYPORT_02_run_msim_rtl_vhdl.do file I found that many file didn't compiled (exp: altera_dp_reconfig_ctrl.v)

2- The DP_SIM folder hadn't the entire file (altera_dp_reconfig_ctrl.v, altera_dp_reset_delay, altera_dp_status_sync).

I am wondring why the quartus messed to include this file in the simulation folder.

Thanks

Hi,

I am trying to implement a converter of an DisplayPort-RX to HDSDI-TX. In the simulation the design has a good functionning but during the synthetise (Place and route) I got an error that told me that the design had HSSI PMA conflicts (The CALCLK must be driven by the same source).

I am aware that the PHY-HDSDI and the PHY-DP have a different frequencies and I thought that the quartus will take this consideration to instantiate a different HSSI for each PHY. But when I got this error I am confiouse. and I thank one of the HSSI is used for RX Display and TX HDSDI and this way the conflit occurs.

Now I am wondring if existe any special contraints to resolve this confilt ?

thanks