DisplayPort Rx IP can't generate stable recover clock in clock recover module.

Hi BCT_Intel

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Thank you for your reply.

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My design is based on example design.

So, it is integrate in the example design.

What do you mean "change the frequency" ?

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Because bitec_clkrec module generates pixel clock as recover clock from rx_ss_clk as reference clock.

If you mean that you don't recommend to change the frequency after finishing sof alignment, it is hard to track clock frequency via Mvid, HTOTAL and rdusedw on DCFIFO.

Also, I confirmed Arria V Eratta sheet.

But I could not find my device (5AGXMB3G4F31I3N) in this table.

I already heard the die revision of this device is D version.

Is this device already fixed ?

Thanks a lot,

​Best regards,