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ymiler's avatar
ymiler
Icon for Contributor rankContributor
2 years ago

Direct interface Bus (DIB)

Hi I would like to generate a behavioral model of the DIB for simulation. However, when I create a DIB IP and click on the 'Generate HDL' icon, part of the output files include gibberish inste...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
2 years ago

Let me know if there is any other concern on this.


ymiler's avatar
ymiler
Icon for Contributor rankContributor
2 years ago

Yes , I have other concern .

I have 2 Q about INTEL instructions regarding the DIB architecture :

Link : https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/reset-architecture.html

1)Quote : "you must track all the dib_ready pins from both dies to determine that both intel Stratix 10GX variants are ready for data transactions"

How can I track all the dib_ready pins from both dies ? How DIE0 get the information about “ready” flag from DIE1 ?

2)Quote : " The reset of the PL (main reset of the design _ should be released only after all the dib_ready_n from all the used dib instances are low"

Why does it relevant the reset of the PL ?

Why DIB depends to the PL ?