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lcy2000's avatar
lcy2000
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Difference between PCIE IP "Configuration Space Bypass" for Arria 10 and "TLP Bypass" for Stratix 10

Hi, Thank you for viewing this thread. Currently I'm doing a tech selection for a custom PCIe switch. Both Arria 10 and Stratix 10 meets my requirements in terms of number of XCVRs, PCIe hard cor...
  • skbeh's avatar
    skbeh
    2 years ago

    Hi Chenyang Li

    I agreed that TLP Bypass(S10) is an acronym to configuration space bypass (A10).

    It allows the implementation of advanced features such as:

    - The upstream port or the downstream port of a switch.

    - A custom implementation of a Transaction Layer to meet specific user requirements.


skbeh's avatar
skbeh
Icon for Contributor rankContributor
2 years ago

Hi Chenyang Li


When the configuration space bypass mode is enabled, users coded their own sets of PCIe configuration registers (including the PCIe Express Capability and Secondary PCI Expess Extended Capability registers). It drives TLPs to the custom Configuration Space.

The IP will bypass the Transaction Layer Configuration Space registers included as

part of the Hard IP, allowing users to substitute a custom Configuration Space implemented in soft logic.


In TLP Bypass mode, all the TLP including the configuration TLP will be exposed to user logic through avst interface, customer can implement the user logics.


Both can pass all well‑formed TLPs to the Application Layer using the Avalon-ST RX interface.