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NSuku1's avatar
NSuku1
Icon for New Contributor rankNew Contributor
7 years ago

Designing data input and control component

Hi,

Im a newbie to FPGA design. Im designing a matrix multiplication component (6X6). The matrix component takes in input and params to calculate the output. The input and params should be read from the BRAM and the output has to be stored in the BRAM memory. The params which is a 6X6 matrix has to be stored in a double buffer where the active values will be placed in a front buffer and the remaining param set will remain the back buffer. I would like to know if the data input, param set has to be designed as a separate components or it has to be within the matrix multiplication component ?

Note: The Serial Rapid IO interface IP core will be writing the input from the processor to the application memory address. The accelerator is supposed to read these values and perform the calculations.

Platform :

Arria 10 dev kit

Host : power PC

Interface : serial rapid IO

Tools : Quartus Prime Pro + HLS compiler

Kindly help me.

Thanks in advance

Nivetha

3 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    ​Hi Nivetha,

    Just would like to check with you if there is any specific DSP or multiplier IP core that you are currently using? Thank you.

  • NSuku1's avatar
    NSuku1
    Icon for New Contributor rankNew Contributor
    7 years ago

    Thank you for your reply. Currently, I'm developing the matrix component using HLS and haven't used any IP core yet.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    ​Hi,

    Thanks for your update. For your information, it is rather difficult for me to comment on a design implementation. However, as I look into the Quartus IP Catalog, I come across this ALTERA_FP_MATRIX_MULT IP. Probably you could explore in this to see if it fit your requirement.

    Thank you.