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Waveform's avatar
Waveform
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6 years ago

Description of QSYS example design IP: PCIe DMA Controller 64/128 bit.

Hello! Please, help me with QSYS example design IP: PCIe DMA Controller 64 bit. I need to make a simple DMA exchange between Arria10 (EP) and CPU (RC) onboard thru PCIe Gen3 x1 link. Because of x1...
scs-kno's avatar
scs-kno
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3 years ago

Any luck with the PCIe DMA Controller 64 (altera_avalon_dma_pci)?

PS: The DMA core is described in Embedded Peripherals IP User Guide in Chapter 30. Adapt TXS connections to read xor write from host memory to a destination.