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I have a requirement to initialize a ROM block used on the Cyclone V FPGA fabric with externally stored values. This ROM block is part of a proprietary core we're developing. The ROM data must be stored prior to boot-up as an encrypted (AES) file on the SD Card or some other device. When the FPGA is configured using an .rbf file, the ROM contents must be read from the separate encrypted file, decrypted with its AES key and loaded into the ROM for use by our core.
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What you are describing is not really a ROM, but it is a RAM whose contents are generated during the boot/powerup process of the FPGA. It will be be written once at initialization so it kind of appears to be a ROM, but really it is not, from the point of view of FPGA design. If you could provide one set of data to load into the memory in the Verilog (or VHDL) source file, and compile with that data, then that would be a ROM. Otherwise what you describe is really a RAM that is to be initialized by your FPGA code during the startup process.
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