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schlee68's avatar
schlee68
Icon for New Contributor rankNew Contributor
2 years ago
Solved

DDR4 use part

Hi- Everyone

I've used Xilinx before.

In Xilinx, PL(FPGA part) and PS(CPU part) are separate.

Of course, you can use it in the PL part and also in the PS part.

Is the question the same in Intel FPGA chips?

More specifically, is there any problem with using it in the PL(FPGA) part?

Thanks!

  • sstrell's avatar
    sstrell
    2 years ago

    Not sure what you mean. If you are referring to a stand-alone FPGA (not an SoC), then you would use one of the EMIF IP to access off-chip DDR4, making use of the resources in the device dedicated to this. If you are talking about an SoC FPGA, then you can implement an EMIF in the FPGA side or via the HPS (hard processor system).

2 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Not sure what you mean. If you are referring to a stand-alone FPGA (not an SoC), then you would use one of the EMIF IP to access off-chip DDR4, making use of the resources in the device dedicated to this. If you are talking about an SoC FPGA, then you can implement an EMIF in the FPGA side or via the HPS (hard processor system).