Forum Discussion
AdzimZM_Altera
Regular Contributor
3 years agoHi senjd,
May I know any update on this thread?
Regards,
Adzim
senjd
New Contributor
3 years agoHi AdzimZM_Intel,
Yes. It is SOC Design.
there is an update over it. It was due to reference clock of the ddr controller. clock was some how not proper with differential signals.
Thanks for your replies.
Thanks,
senjd