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Altera_Forum
Honored Contributor
Honored ContributorDDR3 UNIPHY Master/Slave PLL/DLL's
Are therre any consequencies to setting up two DDR3 UNIPHY interfaces one a master PLL/DLL and the other a slave PLL/DLL? Are the individual nios processors able to perform all calibration independe...
Altera_ForumHonored Contributor
Honored ContributorThe purpose of this feature is as you describe. There should be no issues.
