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Honored Contributor
Honored ContributorDDR3 SDRAM Controller Simulation Walkthrough with UniPHY IP
Has anyone successfully integrated a simulation testbench with the altera_mem_if_ddr3_emif Megawizard into their own design (different port size/width/etc)? Following the Altera guidebook (EMI_...
Altera_ForumHonored Contributor
Honored ContributorThe mismatch in Avalon port can be resolved by re-generating the core and re-generate example design once more. I found the equivalent model at the example design: <DDR3 TOP>_example_sim_e0_if0.vhd, all we have to do is copy all the associate files into the library and replace it to the <DDR3 TOP>.vhd in my own design to run functional simulation.
