DDR3 SDRAM Controller Simulation Walkthrough with UniPHY IP

The mismatch in Avalon port can be resolved by re-generating the core and re-generate example design once more. I found the equivalent model at the example design: <DDR3 TOP>_example_sim_e0_if0.vhd, all we have to do is copy all the associate files into the library and replace it to the <DDR3 TOP>.vhd in my own design to run functional simulation.