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Altera_Forum
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13 years ago

DDR3 IP w/ QII_12.1 Uniphy Stratix V - Simulation - Outputs to Mem Components are X's

Hi, I'm upgrading a working (sim & hardware) Stratix III Uniphy DDR3 controller to Stratix V design using QII_12.1 . The IP I've generated is for a "Quarter-rate" controller (ie 800MHz to the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Working now. I needed the input resets known at time 0, and to have the ucode (HEX files) located in the sim directory.