DDR3 ip controller

Did you also run all the timing constraint files? The IP comes with a few SDC files that often have the wrong paths. This makes some of the synchronizers not get picked up by TimeQuest and because of that some paths wind up killing the synthesis. Often fake paths.

What I did was to first create a task in the SDC file to mark the reset synchronizers:

proc rstsync {path} {

puts "Searching for Reset Synchronizer with path $path"

set_false_path -to

[add_to_collection

[get_pins -nowarn -compatibility_mode -nocase $path|a*]

[get_pins -nowarn -compatibility_mode -nocase $path|clrn]

]

}

# Then I found the reset synchronizers and labeled them:

rstsync {*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*}

rstsync {*|ureset_*|reset_reg[*]}

# Then each time it complained I looked at the RTL that it complained and saw it was usually a two flop synchronizer that had no false path. So i added a false path for each one:

set_false_path -to [get_pins -compatibility_mode {mem_ip_inst|mem_ip_inst|p0|umemphy|uread_datapath|read_buffering[*]*read_enable_r|*}]

set_false_path -to [get_pins -compatibility_mode {mem_ip_inst|mem_ip_inst|p0|umemphy|uread_datapath|read_buffering[*]*read_valid_r|*}]

The names will change from IP to IP. These were the ones I used.