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Well do you even need SoPC Builder? If you've only got one block that's going to interface to the DDR2 memory, you can just create the controller without SoPC builder.
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May I kindly ask to advise me how to do it? I need something similar for my project:
I have two modules:
1. the first module writes to the main memory sequentially,
2. the second reads it randomly or block randomly,
and I am using Terasic DE3 board.
I generated the project with DE3_SystemBuilder and in the main module got many I/O parameters:
////////// DDR2 (J9, DDR2 SO-DIMM) //////////
output DDR2_A;
output DDR2_BA;
output DDR2_CAS_n;
output DDR2_CKE;
inout DDR2_CLK_n;
inout DDR2_CLK_p;
output DDR2_CS_n;
output DDR2_DM;
inout DDR2_DQ;
inout DDR2_DQS_n;
inout DDR2_DQS_p;
output DDR2_ODT;
output DDR2_RAS_n;
output DDR2_SA;
output DDR2_SCL;
inout DDR2_SDA;
output DDR2_WE_n;
What I really need is to convert them to
input ClkRead, ClkWrite; // clocks for read and write instructions
// or one clock with the switch for reading or writing
output ReadReady; // on when the data is ready from the memory
input Address; // depending on the word size,
// but I want to use 4GBytes if possible
inout Data; // can be , or even
I can read with considerably slow rate like 50MHz, but I need the total speed about 12-16GBit/s and due to large memory usage I cannot use internal on FPGA memory since it is only 5.6MBits.
Might somebody help or advise me to solve my task?
Thank you!
Sincerely
Ilghiz
Honored Contributor
