DDR2 vontroller with Uniphy simulation problem

Hello,

this is my first post on this forum and I couldn't find an answer anywhere.

I instantiated the DDR2 controller with UniPhy using the IP-library(Megawizard) (Quartus 15.1) but got an error when trying to simulate it.

The error I get is:

#  405 ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench/F_valid is 'x'#  Break in Module altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench at ../syn/DDR2Ctrl_sim//DDR2Ctrl/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench.v line 498#  Simulation Breakpoint: Break in Module altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench at ../syn/DDR2Ctrl_sim//DDR2Ctrl/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench.v line 498

I found this workaround which sound a bit similar to my problem but isn't: https://www.altera.com/support/support-resources/knowledge-base/solutions/spr388472.html

I think the Problem somehow depends on the signal soft_reset_n because if I leave it asserted ('0'), no eror occurs. If I deassert it the error occurs about 180 ns later.

Could anyone please help me out?

Thank you very much.