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Honored Contributor
Honored ContributorDDR2 SDRAM Controller with ALTMEMPHY Synthesis error
Hi, I am trying to generate a DDR2 SDRAM Controller for a single 128 MB DDR2 chip. QSYS perform a good generation (6 warning wich don't concern the ddr2 Controller) but when i try to synthesis ...
Altera_ForumHonored Contributor
Honored ContributorIt is the easy way out to compile our design, but it is the Qsys Verilog generation at fault here. In Altmem-PHY clocks (and a few other signals) have always been defined as a vector (as there are multiple clocks, clock enables, chip selects and ODTs in the case of DIMM or multi-chip designs).
