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Altera_Forum
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14 years ago

DDR2 SDRAM Controller with ALTMEMPHY Synthesis error

Hi, I am trying to generate a DDR2 SDRAM Controller for a single 128 MB DDR2 chip. QSYS perform a good generation (6 warning wich don't concern the ddr2 Controller) but when i try to synthesis ...
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Altera_Forum
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14 years ago

Thank you!!!

I have replace DDr2's the std_logic_vector(0 downto 0) into std_logic, in the entity declaration generated by QSYS.

End the error is gone!!

Tank you again!