DDR2 SDRAM Controller with ALTMEMPHY Synthesis error

hi again,

I got som feedback from SR and I now manage to compile my project without the error message.

A couple of changes had to be made in the project.

In the toplevel file, where I was using the example HDL found in Qsys (which is used inorder to declare an instance of the Qsys system) I changed :

from:

altmemddr_memory_mem_ras_n : out std_logic;

altmemddr_memory_mem_cas_n : out std_logic;

altmemddr_memory_mem_we_n : out std_logic;

to:

altmemddr_memory_mem_ras_n : out std_logic_vector(0 downto 0);

altmemddr_memory_mem_cas_n : out std_logic_vector(0 downto 0);

altmemddr_memory_mem_we_n : out std_logic_vector(0 downto 0);

In addition, changes need to be made to the <file_name>.v file (your file will have the same name you provided to your QSYS project) which is located in the "synthesis" folder.

For several signals the output and inout wire have to be declared with an [0..0] bracket:

output wire [0:0] altmemddr_memory_mem_odt,

inout wire [0:0] altmemddr_memory_mem_clk,

inout wire [0:0] altmemddr_memory_mem_clk_n,

output wire [0:0] altmemddr_memory_mem_cs_n,

output wire [0:0] altmemddr_memory_mem_cke,

output wire [0:0] altmemddr_memory_mem_ras_n,

output wire [0:0] altmemddr_memory_mem_cas_n,

output wire [0:0] altmemddr_memory_mem_we_n,

regards Saber890