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Altera_Forum
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14 years ago

DDR2 SDRAM Controller with ALTMEMPHY Synthesis error

Hi, I am trying to generate a DDR2 SDRAM Controller for a single 128 MB DDR2 chip. QSYS perform a good generation (6 warning wich don't concern the ddr2 Controller) but when i try to synthesis ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I got exactly the same problem. I did double-check the generated source files and my own top-file and all connections are there. But when I looked in the the RTL-viewer the connections are missing and instead it is driving a '1' on ClkDDR and ClkDDR_n, but also on Odt and Cke and cs_n.

I also filed an SR.